DESIGN     :=  asic_top

pll_cfg:=
clk_cfg:=
Freq:= $(addprefix +, $(pll_cfg), $(clk_cfg))

SIM_TOOL   :=  vcs
WAVE_TOOL  :=  verdi
WAVE_FILE  :=  ${DESIGN}.fsdb

NOVAS    := /eda/tools/snps/verdi/R-2020.12/share/PLI/VCS/LINUX64
EXTRA    := -P ${NOVAS}/novas.tab\
            ${NOVAS}/pli.a

## foundry lib
LIB = -v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp30p140cg.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp30p140hvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp30p140lvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp30p140mblvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp30p140mb.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp30p140opphvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp30p140opplvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp30p140oppuhvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp30p140oppulvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp30p140opp.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp30p140uhvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp30p140ulvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp30p140.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp35p140cghvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp35p140cg.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp35p140hvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp35p140lvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp35p140mbhvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp35p140mblvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp35p140mb.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp35p140opphvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp35p140opplvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp35p140oppuhvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp35p140oppulvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp35p140opp.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp35p140uhvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp35p140ulvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp35p140.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140cgcwhvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140cgcw.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140cgehvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140cghvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140cguhvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140cg.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140ehvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140hvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140lvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140mbhvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140mb.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140oppehvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140opphvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140opplvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140oppuhvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140opp.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140uhvt.v \
         /home/zhuangchunan/proj/soc_proj/soc_final_ysyx4_t28/lib/verilog/./tcbn28hpcplusbwp40p140.v \

## log path
COMP_LOG  :=  -l compile.log
SIM_LOG   :=  -l sim.log

## filelist
RTL_FLIST :=  -f ../filelist/asic_top.f \
              -f ../filelist/amba.f \
              -f ../filelist/core.f \
              -f ../filelist/ip.f

TB_FLIST  :=  -f ../filelist/asic_tblist.f \
              -top asic_system \

NET_PATH  :=  -v netlist/asic_top_LVT.syn.v.gz

SDF_FILE  :=  "../netlist/asic_top_CTS_MAX.sdf"

SIM_INC  :=     +incdir+../top \
                +incdir+../new_ip/clint/rtl \
                +incdir+../new_ip/plic/rtl \
                +incdir+../new_ip/sram/rtl \
                +incdir+../new_ip/uart/rtl \
                +incdir+../new_ip/gpio/rtl \
                +incdir+../new_ip/pwm/rtl \
                +incdir+../new_ip/rtc/rtl \
                +incdir+../new_ip/wdg/rtl \
                +incdir+../new_ip/timer/rtl \
                +incdir+../new_ip/i2c/rtl \
                +incdir+../new_ip/spi/rtl \
                +incdir+../new_ip/vga/rtl \
                +incdir+../new_ip/ps2/rtl \
                +incdir+../new_ip/rng/rtl \
                +incdir+../new_ip/archinfo/rtl \
                +incdir+../new_ip/rcu/rtl \
                +incdir+../new_ip/common/rtl \
                +incdir+../new_ip/common/rtl/clkrst \
                +incdir+../new_ip/common/rtl/cdc \
                +incdir+../new_ip/common/rtl/tech \
                +incdir+../new_ip/common/rtl/interface \
                +incdir+../new_ip/common/rtl/tech \
                +incdir+../old_ip/spiFlash/N25Q128A13E_VG12 \
                +incdir+../old_ip/spiFlash/N25Q128A13E_VG12/include \
                +incdir+../old_ip/spi/rtl \
                +incdir+../old_ip/uart/rtl \
                +incdir+../old_ip/keyboard \
                +incdir+../old_ip/kdb \
                +incdir+../old_ip/sdram/rtl \
                +incdir+../old_ip/sdram/tb \
                +incdir+../old_ip/vga \
                +incdir+../amba/amib_chiplink_slv_axi4_tpv/verilog \
                +incdir+../amba/amib_dma_axi4_cpu/verilog \
                +incdir+../amba/amib_perip0_gp_apb4/verilog \
                +incdir+../amba/amib_perip1_gp_apb4/verilog \
                +incdir+../amba/amib_psram_slv_axi4/verilog \
                +incdir+../amba/amib_sdram_slv_axi4/verilog \
                +incdir+../amba/amib_sram_slv_axi4/verilog \
                +incdir+../amba/amib_sys_gp_apb4/verilog \
                +incdir+../amba/amib_tpv_gp_apb4/verilog \
                +incdir+../amba/apb_bridge/verilog \
                +incdir+../amba/asib_cpu_mst_axi4/verilog \
                +incdir+../amba/asib_vgalcd_mst_axi4/verilog \
                +incdir+../amba/busmatrix_switch2/verilog \
                +incdir+../amba/cdc_blocks/verilog \
                +incdir+../amba/default_slave_ds_1/verilog \
                +incdir+../amba/ib_chiplink_slv_axi4_tpv_ib/verilog \
                +incdir+../amba/ib_dma_axi4_cpu_ib/verilog \
                +incdir+../amba/ib_perip0_gp_apb4_ib/verilog \
                +incdir+../amba/ib_perip1_gp_apb4_ib/verilog \
                +incdir+../amba/ib_psram_slv_axi4_ib/verilog \
                +incdir+../amba/ib_sdram_slv_axi4_ib/verilog \
                +incdir+../amba/ib_sram_slv_axi4_ib/verilog \
                +incdir+../amba/ib_sys_gp_apb4_ib/verilog \
                +incdir+../amba/ib_tpv_gp_apb4_ib/verilog \
                +incdir+../amba/ib_vgalcd_mst_axi4_ib/verilog \
                +incdir+../amba/reg_slice/verilog \
                +incdir+../amba/nic400/verilog/Axi \
                +incdir+../amba/nic400/verilog/Axi4PC \
                +incdir+../amba/nic400/verilog/ApbPC \
                +incdir+../amba/nic400/verilog/Apb4PC \

## vcs option
SIM_OPTIONS     :=  -full64  +v2k -sverilog -timescale=1ns/10ps \
                    ${EXTRA} \
                    -kdb \
                    -debug_acc+all \
                    +error+500 \
                    +vcs+flush+all \
                    +lint=TFIPC-L \
                    +define+no_warning \
                    +define+S50 \
                    +define+SVA_OFF \
                    -work DEFAULT \
                    +define+RANDOMIZE_REG_INIT \
                    ${SIM_INC} \
                    -lSDL2

POST_SIM_OPTION :=  -sdf max:asic_system.u0_asic_top: ${SDF_FILE} \
                    +delay_mode_path \
                    +sdfverbose \
                    +neg_tchk \
                    -negdelay \
                    -diag=sdf:verbose \
                    +warn=OPD:10,IWNF:10,SDFCOM_UHICD:10,SDFCOM_ANICD:10,SDFCOM_NICD:10,DRTZ:10,SDFCOM_UHICD:10,SDFCOM_NTCDTL:10 \

TIME_OPTION     :=  +notimingcheck \
                    +nospecify \


comp:
	${SIM_TOOL} ${SIM_OPTIONS} ${TIME_OPTION} ${RTL_FLIST} ${TB_FLIST} ${COMP_LOG}

net_comp:
	${SIM_TOOL} ${SIM_OPTIONS} ${TIME_OPTION} ${TB_FLIST} ${COMP_LOG} ${NET_PATH}

postnet_comp:
	${SIM_TOOL} ${SIM_OPTIONS} ${POST_SIM_OPTION} ${TB_FLIST} ${COMP_LOG} ${NET_PATH}

sim: comp
	./simv ${SIM_LOG} $(Freq)

wave:
	${WAVE_TOOL} -ssf ${WAVE_FILE} -nologo

.PHONY : clean
clean : 
	rm -fr csrc *simv.daidir* *simv* ucli.key vcdplus.vpd DVEfiles INCA_libs *.fsdb* *.log
